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STMicroelectronics /STM32L4S5 /DSI /DSI_CLTCR

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Interpret as DSI_CLTCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LP2HS_TIME0HS2LP_TIME

Description

DSI Host Clock Lane Timer Configuration Register

Fields

LP2HS_TIME

Low-Power to High-Speed Time
HS2LP_TIME

High-Speed to Low-Power Time

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data