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STMicroelectronics /STM32L4S5 /DSI /DSI_WPCR2

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Interpret as DSI_WPCR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0HSTXDCL 0HSTXDLL 0LPSRCL 0LPSRDL 0 (SDCC)SDCC 0HSTXSRCCL 0HSTXSRCDL 0 (FLPRXLPM)FLPRXLPM 0LPRXFT

Description

DSI Wrapper PHY Configuration Register 2

Fields

HSTXDCL

High-Speed Transmission Delay on Clock Lane
HSTXDLL

High-Speed Transmission Delay on Data Lanes
LPSRCL

Low-Power transmission Slew Rate Compensation on Clock Lane
LPSRDL

Low-Power transmission Slew Rate Compensation on Data Lanes
SDCC

SDD Control
HSTXSRCCL

High-Speed Transmission Slew Rate Control on Clock Lane
HSTXSRCDL

High-Speed Transmission Slew Rate Control on Data Lanes
FLPRXLPM

Forces LP Receiver in Low-Power Mode
LPRXFT

Low-Power RX low-pass Filtering Tuning

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data