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STMicroelectronics /STM32L4S5 /GFXMMU /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B0OIE)B0OIE 0 (B1OIE)B1OIE 0 (B2OIE)B2OIE 0 (B3OIE)B3OIE 0 (AMEIE)AMEIE 0 (BM192)BM192

Description

Graphic MMU configuration register

Fields

B0OIE

Buffer 0 overflow interrupt enable
B1OIE

Buffer 1 overflow interrupt enable
B2OIE

Buffer 2 overflow interrupt enable
B3OIE

Buffer 3 overflow interrupt enable
AMEIE

AHB master error interrupt enable
BM192

192 Block mode

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data