STMicroelectronics /STM32L4S5 /I2C1 /ISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXE)TXE 0 (TXIS)TXIS 0 (RXNE)RXNE 0 (ADDR)ADDR 0 (NACKF)NACKF 0 (STOPF)STOPF 0 (TC)TC 0 (TCR)TCR 0 (BERR)BERR 0 (ARLO)ARLO 0 (OVR)OVR 0 (PECERR)PECERR 0 (TIMEOUT)TIMEOUT 0 (ALERT)ALERT 0 (BUSY)BUSY 0 (DIR)DIR 0ADDCODE

Description

Interrupt and Status register

Fields

TXE

Transmit data register empty (transmitters)

TXIS

Transmit interrupt status (transmitters)

RXNE

Receive data register not empty (receivers)

ADDR

Address matched (slave mode)

NACKF

Not acknowledge received flag

STOPF

Stop detection flag

TC

Transfer Complete (master mode)

TCR

Transfer Complete Reload

BERR

Bus error

ARLO

Arbitration lost

OVR

Overrun/Underrun (slave mode)

PECERR

PEC Error in reception

TIMEOUT

Timeout or t_low detection flag

ALERT

SMBus alert

BUSY

Bus busy

DIR

Transfer direction (Slave mode)

ADDCODE

Address match code (Slave mode)

Links

()