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STMicroelectronics /STM32L4S5 /RCC /AHB1SMENR

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Interpret as AHB1SMENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA1SMEN)DMA1SMEN 0 (DMA2SMEN)DMA2SMEN 0 (DMAMUX1SMEN)DMAMUX1SMEN 0 (FLASHSMEN)FLASHSMEN 0 (SRAM1SMEN)SRAM1SMEN 0 (CRCSMEN)CRCSMEN 0 (TSCSMEN)TSCSMEN 0 (DMA2DSMEN)DMA2DSMEN 0 (GFXMMUSMEN)GFXMMUSMEN

Description

AHB1 peripheral clocks enable in Sleep and Stop modes register

Fields

DMA1SMEN

DMA1 clocks enable during Sleep and Stop modes
DMA2SMEN

DMA2 clocks enable during Sleep and Stop modes
DMAMUX1SMEN

DMAMUX clock enable during Sleep and Stop modes
FLASHSMEN

Flash memory interface clocks enable during Sleep and Stop modes
SRAM1SMEN

SRAM1 interface clocks enable during Sleep and Stop modes
CRCSMEN

CRCSMEN
TSCSMEN

Touch Sensing Controller clocks enable during Sleep and Stop modes
DMA2DSMEN

DMA2D clock enable during Sleep and Stop modes
GFXMMUSMEN

GFXMMU clock enable during Sleep and Stop modes

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data