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STMicroelectronics /STM32L4x2 /DFSDM /CHDATIN0R

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Interpret as CHDATIN0R

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INDAT00INDAT1

Description

channel data input register

Fields

INDAT0

INDAT0
INDAT1

INDAT1

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data