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STMicroelectronics /STM32L4x3 /RCC /PLLSAI1CFGR

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Interpret as PLLSAI1CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLLSAI1N0 (PLLSAI1PEN)PLLSAI1PEN 0 (PLLSAI1P)PLLSAI1P 0 (PLLSAI1QEN)PLLSAI1QEN 0PLLSAI1Q 0 (PLLSAI1REN)PLLSAI1REN 0PLLSAI1R

Description

PLLSAI1 configuration register

Fields

PLLSAI1N

SAI1PLL multiplication factor for VCO
PLLSAI1PEN

SAI1PLL PLLSAI1CLK output enable
PLLSAI1P

SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)
PLLSAI1QEN

SAI1PLL PLLUSB2CLK output enable
PLLSAI1Q

SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)
PLLSAI1REN

PLLSAI1 PLLADC1CLK output enable
PLLSAI1R

PLLSAI1 division factor for PLLADC1CLK (ADC clock)

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data