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STMicroelectronics /STM32L4x3 /TIM1 /OR2

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Interpret as OR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BKINE)BKINE 0 (BKCMP1E)BKCMP1E 0 (BKCMP2E)BKCMP2E 0 (BKDFBK0E)BKDFBK0E 0 (BKINP)BKINP 0 (BKCMP1P)BKCMP1P 0 (BKCMP2P)BKCMP2P 0ETRSEL

Description

DMA address for full transfer

Fields

BKINE

BRK BKIN input enable
BKCMP1E

BRK COMP1 enable
BKCMP2E

BRK COMP2 enable
BKDFBK0E

BRK DFSDM_BREAK0 enable
BKINP

BRK BKIN input polarity
BKCMP1P

BRK COMP1 input polarity
BKCMP2P

BRK COMP2 input polarity
ETRSEL

ETR source selection

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data