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STMicroelectronics /STM32L4x5 /DBGMCU /APB1_FZR1

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Interpret as APB1_FZR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIMER2_STOP)DBG_TIMER2_STOP 0 (DBG_TIM3_STOP)DBG_TIM3_STOP 0 (DBG_TIM4_STOP)DBG_TIM4_STOP 0 (DBG_TIM5_STOP)DBG_TIM5_STOP 0 (DBG_TIMER6_STOP)DBG_TIMER6_STOP 0 (DBG_TIM7_STOP)DBG_TIM7_STOP 0 (DBG_RTC_STOP)DBG_RTC_STOP 0 (DBG_WWDG_STOP)DBG_WWDG_STOP 0 (DBG_IWDG_STOP)DBG_IWDG_STOP 0 (DBG_I2C1_STOP)DBG_I2C1_STOP 0 (DBG_I2C2_STOP)DBG_I2C2_STOP 0 (DBG_I2C3_STOP)DBG_I2C3_STOP 0 (DBG_CAN_STOP)DBG_CAN_STOP 0 (DBG_LPTIMER_STOP)DBG_LPTIMER_STOP

Description

APB Low Freeze Register 1

Fields

DBG_TIMER2_STOP

Debug Timer 2 stopped when Core is halted
DBG_TIM3_STOP

TIM3 counter stopped when core is halted
DBG_TIM4_STOP

TIM4 counter stopped when core is halted
DBG_TIM5_STOP

TIM5 counter stopped when core is halted
DBG_TIMER6_STOP

Debug Timer 6 stopped when Core is halted
DBG_TIM7_STOP

TIM7 counter stopped when core is halted
DBG_RTC_STOP

Debug RTC stopped when Core is halted
DBG_WWDG_STOP

Debug Window Wachdog stopped when Core is halted
DBG_IWDG_STOP

Debug Independent Wachdog stopped when Core is halted
DBG_I2C1_STOP

I2C1 SMBUS timeout mode stopped when core is halted
DBG_I2C2_STOP

I2C2 SMBUS timeout mode stopped when core is halted
DBG_I2C3_STOP

I2C3 SMBUS timeout counter stopped when core is halted
DBG_CAN_STOP

bxCAN stopped when core is halted
DBG_LPTIMER_STOP

LPTIM1 counter stopped when core is halted

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data