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STMicroelectronics /STM32L4x5 /DFSDM /DFSDM0_CR1

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Interpret as DFSDM0_CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DFEN)DFEN 0 (JSWSTART)JSWSTART 0 (JSYNC)JSYNC 0 (JSCAN)JSCAN 0 (JDMAEN)JDMAEN 0JEXTSEL 0JEXTEN 0 (RSWSTART)RSWSTART 0 (RCONT)RCONT 0 (RSYNC)RSYNC 0 (RDMAEN)RDMAEN 0RCH0 (FAST)FAST 0 (AWFSEL)AWFSEL

Description

control register 1

Fields

DFEN

DFSDM enable
JSWSTART

Start a conversion of the injected group of channels
JSYNC

Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
JSCAN

Scanning conversion mode for injected conversions
JDMAEN

DMA channel enabled to read data for the injected channel group
JEXTSEL

Trigger signal selection for launching injected conversions
JEXTEN

Trigger enable and trigger edge selection for injected conversions
RSWSTART

Software start of a conversion on the regular channel
RCONT

Continuous mode selection for regular conversions
RSYNC

Launch regular conversion synchronously with DFSDM0
RDMAEN

DMA channel enabled to read data for the regular conversion
RCH

Regular channel selection
FAST

Fast conversion mode selection for regular conversions
AWFSEL

Analog watchdog fast mode select

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data