RNG control register
| RNGEN | Random number generator enable |
| IE | Interrupt enable |
| CED | Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled. |
| RNG_CONFIG3 | RNG configuration 3 |
| NISTC | Non NIST compliant |
| RNG_CONFIG2 | RNG configuration 2 |
| CLKDIV | Clock divider factor |
| RNG_CONFIG1 | RNG configuration 1 |
| CONDRST | Conditioning soft reset |
| CONFIGLOCK | RNG Config Lock |