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STMicroelectronics /STM32L552 /SAI1 /BCR1

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Interpret as BCR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MODE 0PRTCFG 0DS0 (LSBFIRST)LSBFIRST 0 (CKSTR)CKSTR 0SYNCEN 0 (MONO)MONO 0 (OutDri)OutDri 0 (SAIBEN)SAIBEN 0 (DMAEN)DMAEN 0 (NODIV)NODIV 0MCJDIV0 (OSR)OSR

Description

BConfiguration register 1

Fields

MODE

Audio block mode
PRTCFG

Protocol configuration
DS

Data size
LSBFIRST

Least significant bit first
CKSTR

Clock strobing edge
SYNCEN

Synchronization enable
MONO

Mono mode
OutDri

Output drive
SAIBEN

Audio block B enable
DMAEN

DMA enable
NODIV

No divider
MCJDIV

Master clock divider
OSR

Oversampling ratio for master clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data