AWD1SGL=B_0x0, WAIT=B_0x0, DISCEN=B_0x0, RES=B_0x0, SCANDIR=B_0x0, EXTSEL=B_0x0, AWD1CH=B_0x0, EXTEN=B_0x0, AWD1EN=B_0x0, AUTOFF=B_0x0, ALIGN=B_0x0, DMACFG=B_0x0, DMAEN=B_0x0, CHSELRMOD=B_0x0, CONT=B_0x0, OVRMOD=B_0x0
ADC configuration register 1
| DMAEN | Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333. 0 (B_0x0): DMA disabled 1 (B_0x1): DMA enabled |
| DMACFG | Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN1=11. For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333. 0 (B_0x0): DMA one shot mode selected 1 (B_0x1): DMA circular mode selected |
| SCANDIR | Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared. Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 0 (B_0x0): Upward scan (from CHSEL0 to CHSEL) 1 (B_0x1): Backward scan (from CHSEL to CHSEL0) |
| RES | Data resolution These bits are written by software to select the resolution of the conversion. 0 (B_0x0): 12 bits 1 (B_0x1): 10 bits 2 (B_0x2): 8 bits 3 (B_0x3): 6 bits |
| ALIGN | Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332 0 (B_0x0): Right alignment 1 (B_0x1): Left alignment |
| EXTSEL | External trigger selection These bits select the external event used to trigger the start of conversion (refer to Table160: External triggers for details): 0 (B_0x0): TRG0 1 (B_0x1): TRG1 2 (B_0x2): TRG2 3 (B_0x3): TRG3 4 (B_0x4): TRG4 5 (B_0x5): TRG5 6 (B_0x6): TRG6 7 (B_0x7): TRG7 |
| EXTEN | External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. 0 (B_0x0): Hardware trigger detection disabled (conversions can be started by software) 1 (B_0x1): Hardware trigger detection on the rising edge 2 (B_0x2): Hardware trigger detection on the falling edge 3 (B_0x3): Hardware trigger detection on both the rising and falling edges |
| OVRMOD | Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. 0 (B_0x0): ADC_DR register is preserved with the old data when an overrun is detected. 1 (B_0x1): ADC_DR register is overwritten with the last conversion result when an overrun is detected. |
| CONT | Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11. 0 (B_0x0): Single conversion mode 1 (B_0x1): Continuous conversion mode |
| WAIT | Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. 0 (B_0x0): Wait conversion mode off 1 (B_0x1): Wait conversion mode on |
| AUTOFF | Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. 0 (B_0x0): Auto-off mode disabled 1 (B_0x1): Auto-off mode enabled |
| DISCEN | Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11. 0 (B_0x0): Discontinuous mode disabled 1 (B_0x1): Discontinuous mode enabled |
| CHSELRMOD | Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored. 0 (B_0x0): Each bit of the ADC_CHSELR register enables an input 1 (B_0x1): ADC_CHSELR register is able to sequence up to 8 channels |
| AWD1SGL | Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels 0 (B_0x0): Analog watchdog 1 enabled on all channels 1 (B_0x1): Analog watchdog 1 enabled on a single channel |
| AWD1EN | Analog watchdog enable This bit is set and cleared by software. 0 (B_0x0): Analog watchdog 1 disabled 1 (B_0x1): Analog watchdog 1 enabled |
| AWD1CH | Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. … Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. 0 (B_0x0): ADC analog input Channel 0 monitored by AWD 1 (B_0x1): ADC analog input Channel 1 monitored by AWD 19 (B_0x13): ADC analog input Channel 19 monitored by AWD |