STMicroelectronics /STM32U073 /ADC /ADC_CFGR2

Oversampler Enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared.

0 (B_0x0): Oversampler disabled

1 (B_0x1): Oversampler enabled

Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADEN bit is cleared.

0 (B_0x0): 2x

1 (B_0x1): 4x

2 (B_0x2): 8x

3 (B_0x3): 16x

4 (B_0x4): 32x

5 (B_0x5): 64x

6 (B_0x6): 128x

7 (B_0x7): 256x

Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADEN bit is cleared.

0 (B_0x0): No shift

1 (B_0x1): Shift 1-bit

2 (B_0x2): Shift 2-bits

3 (B_0x3): Shift 3-bits

4 (B_0x4): Shift 4-bits

5 (B_0x5): Shift 5-bits

6 (B_0x6): Shift 6-bits

7 (B_0x7): Shift 7-bits

8 (B_0x8): Shift 8-bits

Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared.

0 (B_0x0): All oversampled conversions for a channel are done consecutively after a trigger

1 (B_0x1): Each oversampled conversion for a channel needs a trigger

Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared.

0 (B_0x0): Low Frequency Trigger Mode disabled

1 (B_0x1): Low Frequency Trigger Mode enabled

ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10).

0 (B_0x0): ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)

1 (B_0x1): PCLK/2 (Synchronous clock mode)

2 (B_0x2): PCLK/4 (Synchronous clock mode)