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STMicroelectronics /STM32U073 /DBGMCU /DBGMCU_APB2FZR

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Interpret as DBGMCU_APB2FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBG_TIM1_STOP 0 (B_0x0)DBG_TIM14_STOP 0 (B_0x0)DBG_TIM15_STOP 0 (B_0x0)DBG_TIM16_STOP 0 (B_0x0)DBG_LPTIM3_STOP

DBG_TIM15_STOP=B_0x0, DBG_LPTIM3_STOP=B_0x0, DBG_TIM1_STOP=B_0x0, DBG_TIM16_STOP=B_0x0, DBG_TIM14_STOP=B_0x0

Description

DBG APB2 freeze register

Fields

DBG_TIM1_STOP

TIM1 stop in debug

0 (B_0x0): normal operation. TIM1 continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. TIM1 is frozen while CPU is in debug mode.
DBG_TIM14_STOP

TIM14 stop in debug

0 (B_0x0): normal operation. TIM14 continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. TIM14 is frozen while CPU is in debug mode.
DBG_TIM15_STOP

TIM15 stop in debug

0 (B_0x0): normal operation. TIM15 continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. TIM15 is frozen while CPU is in debug mode.
DBG_TIM16_STOP

TIM16 stop in debug

0 (B_0x0): normal operation. TIM16 continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. TIM16 is frozen while CPU is in debug mode.
DBG_LPTIM3_STOP

LPTIM3 stop in debug

0 (B_0x0): normal operation. LPTIM3 continues to operate while CPU is in debug mode.

1 (B_0x1): stop in debug. LPTIM3 is frozen while CPU is in debug mode.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data