SWI18=B_0x0, SWI17=B_0x0, SWI15=B_0x0, SWI20=B_0x0, SWI7=B_0x0, SWI3=B_0x0, SWI2=B_0x0, SWI21=B_0x0, SWI1=B_0x0, SWI4=B_0x0, SWI13=B_0x0, SWI5=B_0x0, SWI6=B_0x0, SWI11=B_0x0, SWI19=B_0x0, SWI0=B_0x0, SWI16=B_0x0, SWI14=B_0x0, SWI9=B_0x0, SWI10=B_0x0, SWI12=B_0x0, SWI8=B_0x0
EXTI software interrupt event register 1
| SWI0 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI1 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI2 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI3 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI4 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI5 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI6 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI7 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI8 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI9 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI10 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI11 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI12 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI13 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI14 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI15 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI16 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI17 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI18 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI19 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI20 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |
| SWI21 | Software rising edge event trigger on line x (x1=1211to10) Setting of any bit by software triggers a rising edge event on the corresponding line x, resulting in an interrupt, independently of EXTI_RTSR1 and EXTI_FTSR1 settings. The bits are automatically cleared by HW. Reading of any bit always returns 0. Bits 18 and 19 are available only on STM32U0x3xx devices. They are reserved on STM32U031xx devices. 0 (B_0x0): No effect 1 (B_0x1): Rising edge event generated on the corresponding line, followed by an interrupt |