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STMicroelectronics /STM32U073 /FLASH /FLASH_ECCR

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Interpret as FLASH_ECCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADDR_ECC0 (SYSF_ECC)SYSF_ECC 0 (B_0x0)ECCCIE 0 (ECCC)ECCC 0 (ECCD)ECCD

ECCCIE=B_0x0

Description

FLASH ECC register

Fields

ADDR_ECC

ECC fail double-word address offset In case of ECC error or ECC correction detected, this bitfield contains double-word offset (multiple of 64 bits) to main Flash memory.
SYSF_ECC

System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory.
ECCCIE

ECC correction interrupt enable

0 (B_0x0): ECCC interrupt disabled

1 (B_0x1): ECCC interrupt enabled
ECCC

ECC correction Set by hardware when one ECC error has been detected and corrected. An interrupt is generated if ECCIE is set. Cleared by writing 1.
ECCD

ECC detection Set by hardware when two ECC errors have been detected. When this bit is set, a NMI is generated. Cleared by writing 1.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data