I2C timing register
| SCLL | SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL + 1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings. |
| SCLH | SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH + 1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing. |
| SDADEL | Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing. |
| SCLDEL | Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL + 1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing. |
| PRESC | Timing prescaler This field is used to prescale I2CCLK to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings) and for SCL high and low level counters (refer to I2C master initialization). tPRESC = (PRESC + 1) x tI2CCLK |