ENABLE=B_0x0
LPTIM control register
| ENABLE | LPTIM enable The ENABLE bit is set and cleared by software. 0 (B_0x0): LPTIM is disabled. Writing ‘0’ to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests). 1 (B_0x1): LPTIM is enabled |
| SNGSTRT | LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM3_ARR and LPTIM3_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. |
| CNTSTRT | Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = 00), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than 00), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM3_ARR and LPTIM3_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. |
| COUNTRST | Counter reset This bit is set by software and cleared by hardware. When set to ‘1’ this bit triggers a synchronous reset of the LPTIM3_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to ‘1’ by software before it is already cleared to ‘0’ by hardware. Software must consequently check that COUNTRST bit is already cleared to ‘0’ before attempting to set it to ‘1’. |
| RSTARE | Reset after read enable This bit is set and cleared by software. When RSTARE is set to ‘1’, any read access to LPTIM3_CNT register asynchronously resets LPTIM3_CNT register content. This bit can be set only when the LPTIM is enabled. |