PVDO=B_0x0, PVMO1=B_0x0, PVMO3=B_0x0, VOSF=B_0x0, REGLPS=B_0x0, REGLPF=B_0x0, FLASH_RDY=B_0x0, PVMO4=B_0x0
Power status register 2
| FLASH_RDY | Flash ready flag This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory. 0 (B_0x0): Flash memory in power down 1 (B_0x1): Flash memory ready to be accessed |
| REGLPS | Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased. 0 (B_0x0): The low-power regulator is not ready 1 (B_0x1): The low-power regulator is ready |
| REGLPF | Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready. 0 (B_0x0): The regulator is ready in main mode (MR) 1 (B_0x1): The regulator is in low-power mode (LPR) |
| VOSF | Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register. 0 (B_0x0): The regulator is ready in the selected voltage range 1 (B_0x1): The regulator output voltage is changing to the required voltage level |
| PVDO | Programmable voltage detector output 0 (B_0x0): VDD is above the selected PVD threshold 1 (B_0x1): VDD is below the selected PVD threshold |
| PVMO1 | Peripheral voltage monitoring output: VDDUSB vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time. 0 (B_0x0): VDDUSB voltage is above PVM1 threshold (around 1.21V). 1 (B_0x1): VDDUSB voltage is below PVM1 threshold (around 1.21V). |
| PVMO3 | Peripheral voltage monitoring output: VDDA vs. 1.621V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time. 0 (B_0x0): VDDA voltage is above PVM3 threshold (around 1.621V). 1 (B_0x1): VDDA voltage is below PVM3 threshold (around 1.621V). |
| PVMO4 | Peripheral voltage monitoring output: VDDA vs. 2.21V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time. 0 (B_0x0): VDDA voltage is above PVM4 threshold (around 2.21V). 1 (B_0x1): VDDA voltage is below PVM4 threshold (around 2.21V). |