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STMicroelectronics /STM32U073 /RCC /RCC_APBRSTR2

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Interpret as RCC_APBRSTR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SYSCFGRST 0 (B_0x0)TIM1RST 0 (B_0x0)SPI1RST 0 (B_0x0)USART1RST 0 (B_0x0)TIM15RST 0 (B_0x0)TIM16RST 0 (B_0x0)ADCRST

ADCRST=B_0x0, SPI1RST=B_0x0, SYSCFGRST=B_0x0, TIM15RST=B_0x0, TIM1RST=B_0x0, TIM16RST=B_0x0, USART1RST=B_0x0

Description

APB peripheral reset register 2

Fields

SYSCFGRST

SYSCFG, COMP and VREFBUF reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset SYSCFG + COMP + VREFBUF
TIM1RST

TIM1 timer reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset TIM1 timer
SPI1RST

SPI1 reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset SPI1
USART1RST

USART1 reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset USART1
TIM15RST

TIM15 timer reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset TIM15 timer
TIM16RST

TIM16 timer reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset TIM16 timer
ADCRST

ADC reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset ADC

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data