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STMicroelectronics /STM32U073 /RCC /RCC_CRRCR

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Interpret as RCC_CRRCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HSI48ON 0 (HSI48RDY)HSI48RDY 0HSI48CAL

HSI48ON=B_0x0

Description

RCC clock recovery RC register

Fields

HSI48ON

HSI48 RC oscillator enable(1)

0 (B_0x0): Disable

1 (B_0x1): Enable
HSI48RDY

HSI48 clock ready flag(1) The flag is set when the HSI48 clock is ready for use.
HSI48CAL

HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data