STMicroelectronics /STM32U073 /RNG /RNG_SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RNG_SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DRDY 0 (B_0x0)CECS 0 (B_0x0)SECS 0 (B_0x0)CEIS 0 (B_0x0)SEIS

SEIS=B_0x0, SECS=B_0x0, CECS=B_0x0, DRDY=B_0x0, CEIS=B_0x0

Description

RNG status register

Fields

DRDY

Data ready Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns to 0 until a new random value is generated. Note: The DRDY bit can rise when the peripheral is disabled (RNGEN1=10 in the RNG_CR register). If IE=1 in the RNG_CR register, an interrupt is generated when DRDY1=11.

0 (B_0x0): The RNG_DR register is not yet valid, no random data is available.

1 (B_0x1): The RNG_DR register contains valid random data.

CECS

Clock error current status Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.

0 (B_0x0): The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.

1 (B_0x1): The RNG clock is too slow (fRNGCLK< fHCLK/32).

SECS

Seed error current status Runtime repetition count test failed (noise source has provided more than 24 consecutive bits at a constant value 0 or 1, or more than 32 consecutive occurrence of two bits patterns 01 or 10) Startup or continuous adaptive proportion test on noise source failed. Startup post-processing/conditioning sanity check failed.

0 (B_0x0): No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.

1 (B_0x1): At least one of the following faulty sequences has been detected:

CEIS

Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.

0 (B_0x0): The RNG clock is correct (fRNGCLK> fHCLK/32)

1 (B_0x1): The RNG clock before the internal divider is detected too slow (fRNGCLK< fHCLK/32)

SEIS

Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is used). Writing 1 has no effect. An interrupt is pending if IE = 1 in the RNG_CR register.

0 (B_0x0): No faulty sequence detected

1 (B_0x1): At least one faulty sequence is detected. See SECS bit description for details.

Links

()