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STMicroelectronics /STM32U073 /RTC /RTC_ALRABINR

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Interpret as RTC_ALRABINR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SS

Description

RTC alarm A binary mode register

Fields

SS

Synchronous counter alarm value in Binary mode This value is compared with the contents of the synchronous counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMASSRR, and so can also be read or written through RTC_ALRMASSR.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data