MASKSS=B_0x0, SSCLR=B_0x0
RTC alarm A subsecond register
| SS | Subseconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. This field is the mirror of SS[14:0] in the RTC_ALRABINR, and so can also be read or written through RTC_ALRABINR. |
| MASKSS | Mask the most-significant bits starting at this bit … From 32 to 63: All 32 SS bits are compared and must match to activate alarm. Note: In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. These bits can be different from 0 only after a shift operation. 0 (B_0x0): No comparison on subseconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1 (B_0x1): SS[31:1] are dont care in Alarm A comparison. Only SS[0] is compared. |
| SSCLR | Clear synchronous counter on alarm (Binary mode only) Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11). 0 (B_0x0): The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. 1 (B_0x1): The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF1FFFF to RTC_ALRABINR.SS[31:0] value and is automatically reloaded with 0xFFFF1FFFF one ck_apre cycle after reaching RTC_ALRABINR.SS[31:0]. |