STMicroelectronics /STM32U073 /RTC /RTC_CR

ck_wut wake-up clock selection 10x: ck_spre (usually 11Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. 11x: ck_spre (usually 1 Hz) clock is selected in BCD mode. In binary or mixed mode, this is the clock selected by BCDU. Furthermore, 2¹⁶ is added to the WUT counter value.

0 (B_0x0): RTC/16 clock is selected

1 (B_0x1): RTC/8 clock is selected

2 (B_0x2): RTC/4 clock is selected

3 (B_0x3): RTC/2 clock is selected

Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.

0 (B_0x0): RTC_TS input rising edge generates a timestamp event

1 (B_0x1): RTC_TS input falling edge generates a timestamp event

RTC_REFIN reference clock detection enable (50 or 601Hz) Note: BIN must be 0x00 and PREDIV_S must be 0x00FF.

0 (B_0x0): RTC_REFIN detection disabled

1 (B_0x1): RTC_REFIN detection enabled

Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.

0 (B_0x0): Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles.

1 (B_0x1): Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters.

Hour format

0 (B_0x0): 24 hour/day format

1 (B_0x1): AM/PM hour format

SSR underflow interrupt enable

0 (B_0x0): SSR underflow interrupt disabled

1 (B_0x1): SSR underflow interrupt enabled

Alarm A enable

0 (B_0x0): Alarm A disabled

1 (B_0x1): Alarm A enabled

Alarm B enable

0 (B_0x0): Alarm B disabled

1 (B_0x1): Alarm B enabled

Wake-up timer enable Note: When the wake-up timer is disabled, wait for WUTWF = 1 before enabling it again.

0 (B_0x0): Wake-up timer disabled

1 (B_0x1): Wake-up timer enabled

timestamp enable

0 (B_0x0): timestamp disable

1 (B_0x1): timestamp enable

Alarm A interrupt enable

0 (B_0x0): Alarm A interrupt disabled

1 (B_0x1): Alarm A interrupt enabled

Alarm B interrupt enable

0 (B_0x0): Alarm B interrupt disable

1 (B_0x1): Alarm B interrupt enable

Wake-up timer interrupt enable

0 (B_0x0): Wake-up timer interrupt disabled

1 (B_0x1): Wake-up timer interrupt enabled

Timestamp interrupt enable

0 (B_0x0): Timestamp interrupt disable

1 (B_0x1): Timestamp interrupt enable

Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.

0 (B_0x0): No effect

1 (B_0x1): Adds 1 hour to the current time. This can be used for summer time change

Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.

0 (B_0x0): No effect

1 (B_0x1): Subtracts 1 hour to the current time. This can be used for winter time change.

Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.

Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.7681kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section128.3.16: Calibration clock output.

0 (B_0x0): Calibration output is 5121Hz

1 (B_0x1): Calibration output is 11Hz

Output polarity This bit is used to configure the polarity of TAMPALRM output.

0 (B_0x0): The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).

1 (B_0x1): The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).

Output selection These bits are used to select the flag to be routed to TAMPALRM output.

0 (B_0x0): Output disabled

1 (B_0x1): Alarm A output enabled

2 (B_0x2): Alarm B output enabled

3 (B_0x3): Wake-up output enabled

Calibration output enable This bit enables the CALIB output

0 (B_0x0): Calibration output disabled

1 (B_0x1): Calibration output enabled

timestamp on internal event enable

0 (B_0x0): internal event timestamp disabled

1 (B_0x1): internal event timestamp enabled

Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set up to 3 ck_apre cycles after the tamper flags. Note: TAMPTS must be cleared before entering RTC initialization mode.

0 (B_0x0): Tamper detection event does not cause a RTC timestamp to be saved

1 (B_0x1): Save RTC timestamp on tamper detection event

Tamper detection output enable on TAMPALRM

0 (B_0x0): The tamper flag is not routed on TAMPALRM

1 (B_0x1): The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL.

Alarm A flag automatic clear

0 (B_0x0): Alarm A event generates a trigger event and ALRAF must be cleared by software to allow next alarm event.

1 (B_0x1): Alarm A event generates a trigger event. ALRAF is automatically cleared by hardware after 1 ck_apre cycle.

Alarm B flag automatic clear

0 (B_0x0): Alarm B event generates a trigger event and ALRBF must be cleared by software to allow next alarm event.

1 (B_0x1): Alarm B event generates a trigger event. ALRBF is automatically cleared by hardware after 1 ck_apre cycle.

TAMPALRM pull-up enable

0 (B_0x0): No pull-up is applied on TAMPALRM output

1 (B_0x1): A pull-up is applied on TAMPALRM output

TAMPALRM output type

0 (B_0x0): TAMPALRM is push-pull output

1 (B_0x1): TAMPALRM is open-drain output

RTC_OUT2 output enable