FRXTH=B_0x0, TXDMAEN=B_0x0, SSOE=B_0x0, RXNEIE=B_0x0, FRF=B_0x0, RXDMAEN=B_0x0, NSSP=B_0x0, DS=B_0x0, LDMA_TX=B_0x0, TXEIE=B_0x0, ERRIE=B_0x0, LDMA_RX=B_0x0
SPI control register 2
| RXDMAEN | Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set. 0 (B_0x0): Rx buffer DMA disabled 1 (B_0x1): Rx buffer DMA enabled |
| TXDMAEN | Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set. 0 (B_0x0): Tx buffer DMA disabled 1 (B_0x1): Tx buffer DMA enabled |
| SSOE | SS output enable Note: This bit is not used in SPI TI mode. 0 (B_0x0): SS output is disabled in master mode and the SPI interface can work in multimaster configuration 1 (B_0x1): SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. |
| NSSP | NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1, or FRF = 1. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). Note: 2. This bit is not used in SPI TI mode. 0 (B_0x0): No NSS pulse 1 (B_0x1): NSS pulse generated |
| FRF | Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). 0 (B_0x0): SPI Motorola mode |
| ERRIE | Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 0 (B_0x0): Error interrupt is masked 1 (B_0x1): Error interrupt is enabled |
| RXNEIE | RX buffer not empty interrupt enable 0 (B_0x0): RXNE interrupt masked 1 (B_0x1): RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. |
| TXEIE | Tx buffer empty interrupt enable 0 (B_0x0): TXE interrupt masked 1 (B_0x1): TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. |
| DS | Data size These bits configure the data length for SPI transfers. If software attempts to write one of the Not used values, they are forced to the value 0111 (8-bit) 0 (B_0x0): Not used 1 (B_0x1): Not used 2 (B_0x2): Not used 3 (B_0x3): 4-bit 4 (B_0x4): 5-bit 5 (B_0x5): 6-bit 6 (B_0x6): 7-bit 7 (B_0x7): 8-bit 8 (B_0x8): 9-bit 9 (B_0x9): 10-bit 10 (B_0xA): 11-bit 11 (B_0xB): 12-bit 12 (B_0xC): 13-bit 13 (B_0xD): 14-bit 14 (B_0xE): 15-bit 15 (B_0xF): 16-bit |
| FRXTH | FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event 0 (B_0x0): RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) 1 (B_0x1): RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) |
| LDMA_RX | Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to Procedure for disabling the SPI on page1954 if the CRCEN bit is set. 0 (B_0x0): Number of data to transfer is even 1 (B_0x1): Number of data to transfer is odd |
| LDMA_TX | Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to Procedure for disabling the SPI on page1954 if the CRCEN bit is set. 0 (B_0x0): Number of data to transfer is even 1 (B_0x1): Number of data to transfer is odd |