STMicroelectronics /STM32U073 /TIM1 /TIM1_BDTR

Dead-time generator setup

Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

0 (B_0x0): LOCK OFF - No bit is write protected.

1 (B_0x1): LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written.

2 (B_0x2): LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.

3 (B_0x3): LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state).

1 (B_0x1): When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output.

Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state).

1 (B_0x1): When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).

Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BRK sources, as per Figure1152: Break and Break2 circuitry overview). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

0 (B_0x0): Break function disabled

1 (B_0x1): Break function enabled

Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

0 (B_0x0): Break input BRK is active low

1 (B_0x1): Break input BRK is active high

Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): MOE can be set only by software

1 (B_0x1): MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (Section122.4.11: TIM1 capture/compare enable register (TIM1_CCER)).

0 (B_0x0): In response to a break 2 event. OC and OCN outputs are disabled

1 (B_0x1): OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register).

Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): No filter, BRK acts asynchronously

1 (B_0x1): f_SAMPLING=f_{CK_INT}, N=2

2 (B_0x2): f_SAMPLING=f_{CK_INT}, N=4

3 (B_0x3): f_SAMPLING=f_{CK_INT}, N=8

4 (B_0x4): f_SAMPLING=f_DTS/2, N=6

5 (B_0x5): f_SAMPLING=f_DTS/2, N=8

6 (B_0x6): f_SAMPLING=f_DTS/4, N=6

7 (B_0x7): f_SAMPLING=f_DTS/4, N=8

8 (B_0x8): f_SAMPLING=f_DTS/8, N=6

9 (B_0x9): f_SAMPLING=f_DTS/8, N=8

10 (B_0xA): f_SAMPLING=f_DTS/16, N=5

11 (B_0xB): f_SAMPLING=f_DTS/16, N=6

12 (B_0xC): f_SAMPLING=f_DTS/16, N=8

13 (B_0xD): f_SAMPLING=f_DTS/32, N=5

14 (B_0xE): f_SAMPLING=f_DTS/32, N=6

15 (B_0xF): f_SAMPLING=f_DTS/32, N=8

Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).

0 (B_0x0): No filter, BRK2 acts asynchronously

1 (B_0x1): f_SAMPLING=f_{CK_INT}, N=2

2 (B_0x2): f_SAMPLING=f_{CK_INT}, N=4

3 (B_0x3): f_SAMPLING=f_{CK_INT}, N=8

4 (B_0x4): f_SAMPLING=f_DTS/2, N=6

5 (B_0x5): f_SAMPLING=f_DTS/2, N=8

6 (B_0x6): f_SAMPLING=f_DTS/4, N=6

7 (B_0x7): f_SAMPLING=f_DTS/4, N=8

8 (B_0x8): f_SAMPLING=f_DTS/8, N=6

9 (B_0x9): f_SAMPLING=f_DTS/8, N=8

10 (B_0xA): f_SAMPLING=f_DTS/16, N=5

11 (B_0xB): f_SAMPLING=f_DTS/16, N=6

12 (B_0xC): f_SAMPLING=f_DTS/16, N=8

13 (B_0xD): f_SAMPLING=f_DTS/32, N=5

14 (B_0xE): f_SAMPLING=f_DTS/32, N=6

15 (B_0xF): f_SAMPLING=f_DTS/32, N=8

Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

0 (B_0x0): Break input BRK2 disabled

1 (B_0x1): Break input BRK2 enabled

Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

0 (B_0x0): Break input BRK2 is active low

1 (B_0x1): Break input BRK2 is active high

Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

0 (B_0x0): Break input BRK is armed

1 (B_0x1): Break input BRK is disarmed

Break2 Disarm Refer to BKDSRM description

Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.

0 (B_0x0): Break input BRK in input mode

1 (B_0x1): Break input BRK in bidirectional mode

Break2 bidirectional Refer to BKBID description