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STMicroelectronics /STM32U073 /TIM1 /TIM1_CCMR3

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Interpret as TIM1_CCMR3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OC5FE)OC5FE 0 (OC5PE)OC5PE 0OC5M0 (OC5CE)OC5CE 0 (OC6FE)OC6FE 0 (OC6PE)OC6PE 0OC6M0 (OC6CE)OC6CE 0 (OC5M_1)OC5M_1 0 (OC6M_1)OC6M_1

Description

TIM1 capture/compare mode register 3

Fields

OC5FE

Output compare 5 fast enable Refer to OC1FE description.
OC5PE

Output compare 5 preload enable Refer to OC1PE description.
OC5M

OC5M[0]: Output compare 5 mode Refer to OC1M description.
OC5CE

Output compare 5 clear enable Refer to OC1CE description.
OC6FE

Output compare 6 fast enable Refer to OC1FE description.
OC6PE

Output compare 6 preload enable Refer to OC1PE description.
OC6M

OC6M[0]: Output compare 6 mode Refer to OC1M description.
OC6CE

Output compare 6 clear enable Refer to OC1CE description.
OC5M_1

OC5M[3]
OC6M_1

OC6M[3]

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data