Regviz

STMicroelectronics /STM32U073 /TIM1 /TIM1_DMAR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIM1_DMAR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/STMicroelectronics/STM32U575/TIM1/TIM1_DMAR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMAB

Description

TIM1 DMA address for full transfer

Fields

DMAB

DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data