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STMicroelectronics /STM32U073 /TSC /TSC_ISR

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Interpret as TSC_ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EOAF 0 (B_0x0)MCEF

MCEF=B_0x0, EOAF=B_0x0

Description

TSC interrupt status register

Fields

EOAF

End of acquisition flag This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits of all enabled analog I/O groups are set or when a max count error is detected). It is cleared by software writing 1 to the bit EOAIC of the TSC_ICR register.

0 (B_0x0): Acquisition is ongoing or not started

1 (B_0x1): Acquisition is complete
MCEF

Max count error flag This bit is set by hardware as soon as an analog I/O group counter reaches the max count value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register.

0 (B_0x0): No max count error (MCE) detected

1 (B_0x1): Max count error (MCE) detected

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data