STMicroelectronics /STM32U073 /USART1 /USART_CR1

USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value.

0 (B_0x0): USART prescaler and outputs disabled, low-power mode

1 (B_0x1): USART enabled

USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode, and clear it when exiting low-power mode.

0 (B_0x0): USART not able to wake up the MCU from low-power mode.

1 (B_0x1): USART able to wake up the MCU from low-power mode.

Receiver enable This bit enables the receiver. It is set and cleared by software.

0 (B_0x0): Receiver is disabled

1 (B_0x1): Receiver is enabled and begins searching for a start bit

Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.

0 (B_0x0): Transmitter is disabled

1 (B_0x1): Transmitter is enabled

IDLE interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated whenever IDLE=1 in the USART_ISR register

RXFIFO not empty interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated whenever ORE=1 or RXFNE=1 in the USART_ISR register

Transmission complete interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated whenever TC=1 in the USART_ISR register

TXFIFO not full interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated whenever TXFNF =1 in the USART_ISR register

PE interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated whenever PE=1 in the USART_ISR register

Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): Even parity

1 (B_0x1): Odd parity

Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): Parity control disabled

1 (B_0x1): Parity control enabled

Receiver wake-up method This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): Idle line

1 (B_0x1): Address mark

Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE=0).

Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.

0 (B_0x0): Receiver in Active mode permanently

1 (B_0x1): Receiver can switch between Mute mode and Active mode.

Character match interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated when the CMF bit is set in the USART_ISR register.

Oversampling mode This bit can only be written when the USART is disabled (UE=0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.

0 (B_0x0): Oversampling by 16

1 (B_0x1): Oversampling by 8

Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE=0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section131.4: USART implementation on page1826.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated when the RTOF bit is set in the USART_ISR register.

End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated when the EOBF flag is set in the USART_ISR register

Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00: 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01: 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE=0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported.

FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0). Note: FIFO mode can be used on standard UART communication, in SPI Master/Slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.

0 (B_0x0): FIFO mode is disabled.

1 (B_0x1): FIFO mode is enabled.

TXFIFO empty interrupt enable This bit is set and cleared by software.

0 (B_0x0): Interrupt inhibited

1 (B_0x1): USART interrupt generated when TXFE=1 in the USART_ISR register

None