STMicroelectronics /STM32U073 /USART1 /USART_CR2

Synchronous Slave mode enable When the SLVEN bit is set, the Synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): Slave mode disabled.

1 (B_0x1): Slave mode enabled.

When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): SPI slave selection depends on NSS input pin.

1 (B_0x1): SPI slave is always selected and NSS input pin is ignored.

7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE=0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.

0 (B_0x0): 4-bit address detection

1 (B_0x1): 7-bit address detection (in 8-bit data mode)

LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): 10-bit break detection

1 (B_0x1): 11-bit break detection

LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): Interrupt is inhibited

1 (B_0x1): An interrupt is generated whenever LBDF=1 in the USART_ISR register

Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in Synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): The clock pulse of the last data bit is not output to the CK pin

1 (B_0x1): The clock pulse of the last data bit is output to the CK pin

Clock phase This bit is used to select the phase of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure1233 and Figure1234) This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): The first clock transition is the first data capture edge

1 (B_0x1): The second clock transition is the first data capture edge

Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in Synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE=0). Note: If Synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): Steady low value on CK pin outside transmission window

1 (B_0x1): Steady high value on CK pin outside transmission window

Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE=0). Note: If neither Synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1

0 (B_0x0): CK pin disabled

1 (B_0x1): CK pin enabled

stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): 1 stop bit

1 (B_0x1): 0.5 stop bit.

2 (B_0x2): 2 stop bits

3 (B_0x3): 1.5 stop bits

LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE=0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): LIN mode disabled

1 (B_0x1): LIN mode enabled

Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): TX/RX pins are used as defined in standard pinout

1 (B_0x1): The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.

RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): RX pin signal works using the standard logic levels (V_DD =1/idle, Gnd=0/mark)

1 (B_0x1): RX pin signal values are inverted. ((V_DD =0/mark, Gnd=1/idle).

TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): TX pin signal works using the standard logic levels (V_DD =1/idle, Gnd=0/mark)

1 (B_0x1): TX pin signal values are inverted. ((V_DD =0/mark, Gnd=1/idle).

Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)

1 (B_0x1): Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.

Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE=0).

0 (B_0x0): data is transmitted/received with data bit 0 first, following the start bit.

1 (B_0x1): data is transmitted/received with the MSB (bit 7/8) first, following the start bit.

Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): Auto baud rate detection is disabled.

1 (B_0x1): Auto baud rate detection is enabled.

Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE=0). Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): Measurement of the start bit is used to detect the baud rate.

1 (B_0x1): Falling edge to falling edge measurement (the received frame must start with a single bit = 1 -> Frame = Start10xxxxxx)

2 (B_0x2): 0x7F frame detection.

3 (B_0x3): 0x55 frame detection

Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section131.4: USART implementation on page1826.

0 (B_0x0): Receiver timeout feature disabled.

1 (B_0x1): Receiver timeout feature enabled.

Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE1=10) or when the USART is disabled (UE1=10).