USBRST=B_0x0_DEVICE_MODE, RST_DCONM=B_0x0, ESOFM=B_0x0, SUSPM=B_0x0, CTRM=B_0x0, SUSPRDY=B_0x0, L1REQM=B_0x0, SOFM=B_0x0, HOST=B_0x0, SUSPEN=B_0x0_DEVICE_MODE, WKUPM=B_0x0, DDISCM=B_0x0, ERRM=B_0x0, L2RES=B_0x0, L1RES=B_0x0, THR512M=B_0x0, PMAOVRM=B_0x0, PDWN=B_0x0
USB control register
| USBRST | USB Reset Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RST_DCON bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RST_DCON interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software. 0 (B_0x0_DEVICE_MODE): No effect 1 (B_0x1_DEVICE_MODE): USB core is under reset |
| PDWN | Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used. 0 (B_0x0): Exit power down 1 (B_0x1): Enter power down mode |
| SUSPRDY | Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wake-up logic and single ended receiver is kept alive to detect remote wake-up or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set. 0 (B_0x0): Normal operation 1 (B_0x1): Suspend state |
| SUSPEN | Suspend state enable Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 31ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY1=11 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Software can set this bit when host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to pursue more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. 0 (B_0x0_DEVICE_MODE): No effect 1 (B_0x1_DEVICE_MODE): Enter L1/L2 suspend |
| L2RES | L2 remote wake-up / resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the host. It must be activated, according to USB specifications, for no less than 11ms and no more than 151ms after which the host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. 0 (B_0x0): No effect 1 (B_0x1): Send L2 resume signaling to device |
| L1RES | L1 remote wake-up / resume driver 0 (B_0x0): No effect 1 (B_0x1): send 50 micro s remote wake up signaling to host |
| L1REQM | LPM L1 state request interrupt mask 0 (B_0x0): LPM L1 state request (L1REQ) interrupt disabled. 1 (B_0x1): L1REQ interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| ESOFM | Expected start of frame interrupt mask 0 (B_0x0): Expected start of frame (ESOF) interrupt disabled. 1 (B_0x1): ESOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| SOFM | Start of frame interrupt mask 0 (B_0x0): SOF interrupt disabled. 1 (B_0x1): SOF interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| RST_DCONM | USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask 0 (B_0x0): RESET interrupt disabled. 1 (B_0x1): RESET interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| SUSPM | Suspend mode interrupt mask 0 (B_0x0): Suspend mode request (SUSP) interrupt disabled. 1 (B_0x1): SUSP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| WKUPM | Wake-up interrupt mask 0 (B_0x0): WKUP interrupt disabled. 1 (B_0x1): WKUP interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| ERRM | Error interrupt mask 0 (B_0x0): ERR interrupt disabled. 1 (B_0x1): ERR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| PMAOVRM | Packet memory area over / underrun interrupt mask 0 (B_0x0): PMAOVR interrupt disabled. 1 (B_0x1): PMAOVR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| CTRM | Correct transfer interrupt mask 0 (B_0x0): Correct transfer (CTR) interrupt disabled. 1 (B_0x1): CTR interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. |
| THR512M | 512 byte threshold interrupt mask 0 (B_0x0): 512 byte threshold interrupt disabled 1 (B_0x1): 512 byte threshold interrupt enabled |
| DDISCM | Device disconnection mask Host mode 0 (B_0x0): Device disconnection interrupt disabled 1 (B_0x1): Device disconnection interrupt enabled |
| HOST | HOST mode HOST bit selects betweens host or device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit. 0 (B_0x0): USB Device function 1 (B_0x1): USB host function (Reserved, host function is not available in these products, see Section134.3: USB implementation) |