OVRIE=B_0x0, CCRDYIE=B_0x0, EOCALIE=B_0x0, AWD3IE=B_0x0, EOSMPIE=B_0x0, EOCIE=B_0x0, EOSIE=B_0x0, AWD1IE=B_0x0, AWD2IE=B_0x0, ADRDYIE=B_0x0
ADC interrupt enable register
| ADRDYIE | ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): ADRDY interrupt disabled. 1 (B_0x1): ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. |
| EOSMPIE | End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): EOSMP interrupt disabled. 1 (B_0x1): EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. |
| EOCIE | End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): EOC interrupt disabled 1 (B_0x1): EOC interrupt enabled. An interrupt is generated when the EOC bit is set. |
| EOSIE | End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): EOS interrupt disabled 1 (B_0x1): EOS interrupt enabled. An interrupt is generated when the EOS bit is set. |
| OVRIE | Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): Overrun interrupt disabled 1 (B_0x1): Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. |
| AWD1IE | Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): Analog watchdog interrupt disabled 1 (B_0x1): Analog watchdog interrupt enabled |
| AWD2IE | Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): Analog watchdog interrupt disabled 1 (B_0x1): Analog watchdog interrupt enabled |
| AWD3IE | Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): Analog watchdog interrupt disabled 1 (B_0x1): Analog watchdog interrupt enabled |
| EOCALIE | End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): End of calibration interrupt disabled 1 (B_0x1): End of calibration interrupt enabled |
| CCRDYIE | Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing). 0 (B_0x0): Channel configuration ready interrupt disabled 1 (B_0x1): Channel configuration ready interrupt enabled |