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STMicroelectronics /STM32U083 /DAC /DAC_SHRR

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Interpret as DAC_SHRR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TREFRESH1

Description

DAC sample and hold refresh time register

Fields

TREFRESH1

DAC channel1 refresh time (only valid in Sample and hold mode) Refresh time1=1(TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN11=10.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data