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STMicroelectronics /STM32U083 /EXTI /EXTI_IMR2

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Interpret as EXTI_IMR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)IM32 0 (B_0x0)IM33 0 (B_0x0)IM34 0 (B_0x0)IM35 0 (B_0x0)IM36 0 (B_0x0)IM37

IM36=B_0x0, IM32=B_0x0, IM37=B_0x0, IM35=B_0x0, IM33=B_0x0, IM34=B_0x0

Description

EXTI CPU wake-up with interrupt mask register

Fields

IM32

CPU wake-up with interrupt mask on line x (x1=1371to132) Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt request from Line x is masked

1 (B_0x1): wake-up with interrupt request from Line x is unmasked
IM33

CPU wake-up with interrupt mask on line x (x1=1371to132) Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt request from Line x is masked

1 (B_0x1): wake-up with interrupt request from Line x is unmasked
IM34

CPU wake-up with interrupt mask on line x (x1=1371to132) Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt request from Line x is masked

1 (B_0x1): wake-up with interrupt request from Line x is unmasked
IM35

CPU wake-up with interrupt mask on line x (x1=1371to132) Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt request from Line x is masked

1 (B_0x1): wake-up with interrupt request from Line x is unmasked
IM36

CPU wake-up with interrupt mask on line x (x1=1371to132) Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt request from Line x is masked

1 (B_0x1): wake-up with interrupt request from Line x is unmasked
IM37

CPU wake-up with interrupt mask on line x (x1=1371to132) Setting/clearing this bit unmasks/masks the CPU wake-up with interrupt, by an event on the corresponding line. Bit IM36 is available only on STM32U0x3xx devices, it is reserved on STM32U031xx devices.

0 (B_0x0): wake-up with interrupt request from Line x is masked

1 (B_0x1): wake-up with interrupt request from Line x is unmasked

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data