DBG_SWEN=B_0x0, EMPTY=B_0x0, LATENCY=B_0x0, PRFTEN=B_0x0, ICEN=B_0x0, ICRST=B_0x0
FLASH access control register
| LATENCY | Flash memory access latency The value in this bitfield represents the number of CPU wait states when accessing the flash memory. Other: Reserved A new write into the bitfield becomes effective when it returns the same value upon read. 0 (B_0x0): Zero wait states 1 (B_0x1): One wait state |
| PRFTEN | CPU Prefetch enable 0 (B_0x0): CPU Prefetch disabled 1 (B_0x1): CPU Prefetch enabled |
| ICEN | CPU Instruction cache enable 0 (B_0x0): CPU Instruction cache is disabled 1 (B_0x1): CPU Instruction cache is enabled |
| ICRST | CPU Instruction cache reset This bit can be written only when the instruction cache is disabled. 0 (B_0x0): CPU Instruction cache is not reset 1 (B_0x1): CPU Instruction cache is reset |
| EMPTY | Main flash memory area empty This bit indicates whether the first location of the main flash memory area is erased or has a programmed value. The bit can be set and reset by software. 0 (B_0x0): Main flash memory area programmed 1 (B_0x1): Main flash memory area empty |
| DBG_SWEN | Debug access software enable Software may use this bit to enable/disable the debugger read access. 0 (B_0x0): Debugger disabled 1 (B_0x1): Debugger enabled |