BORR_LEV=B_0x0, BKPSRAM_HW_ERASE_DISABLE=B_0x0, NRST_STDBY=B_0x0, WWDG_SW=B_0x0, IRHEN=B_0x0, NBOOT_SEL=B_0x0, BDRST=B_0x0, NRST_STOP=B_0x0, NBOOT0=B_0x0, RAM_PARITY_CHECK=B_0x0, NRST_SHDW=B_0x0, IWDG_STOP=B_0x0, IWDG_SW=B_0x0, IWDG_STDBY=B_0x0
FLASH option register
| RDP | Read protection level Other: Level 1, memories read protection active 170 (B_0xAA): Level 0, read protection not active 204 (B_0xCC): Level 2, chip read protection active |
| BORR_LEV | BOR reset level 0 (B_0x0): BOR rising level 1 with threshold around 2.1 V 1 (B_0x1): BOR rising level 2 with threshold around 2.3 V 2 (B_0x2): BOR rising level 3 with threshold around 2.6 V 3 (B_0x3): BOR rising level 4 with threshold around 2.9 V |
| NRST_STOP | Reset generated when entering Stop mode 0 (B_0x0): Reset generated when entering the Stop mode 1 (B_0x1): No reset generated when entering the Stop mode |
| NRST_STDBY | Reset generated when entering Standby mode 0 (B_0x0): Reset generated when entering the Standby mode 1 (B_0x1): No reset generate when entering the Standby mode |
| NRST_SHDW | Reset generated when entering Shutdown mode 0 (B_0x0): Reset generated when entering the Shutdown mode 1 (B_0x1): No reset generated when entering the Shutdown mode |
| IWDG_SW | Independent watchdog selection 0 (B_0x0): Hardware independent watchdog 1 (B_0x1): Software independent watchdog |
| IWDG_STOP | Independent watchdog counter freeze in Stop mode 0 (B_0x0): Independent watchdog counter is frozen in Stop mode 1 (B_0x1): Independent watchdog counter is running in Stop mode |
| IWDG_STDBY | Independent watchdog counter freeze in Standby mode 0 (B_0x0): Independent watchdog counter is frozen in Standby mode 1 (B_0x1): Independent watchdog counter is running in Standby mode |
| WWDG_SW | Window watchdog selection 0 (B_0x0): Hardware window watchdog 1 (B_0x1): Software window watchdog |
| BDRST | Backup domain reset 0 (B_0x0): Enable 1 (B_0x1): Disable |
| RAM_PARITY_CHECK | SRAM parity check control enable/disable 0 (B_0x0): Enable 1 (B_0x1): Disable |
| BKPSRAM_HW_ERASE_DISABLE | Backup SRAM erase prevention 0 (B_0x0): Disable 1 (B_0x1): Enable |
| NBOOT_SEL | BOOT0 signal source selection This option bit defines the source of the BOOT0 signal. 0 (B_0x0): BOOT0 pin (legacy mode) 1 (B_0x1): NBOOT0 option bit |
| NBOOT1 | Boot configuration Together with the BOOT0 pin or option bit NBOOT0 (depending on NBOOT_SEL option bit configuration), this bit selects boot mode from the main flash memory, SRAM or the system memory. Refer to Section12.5: Boot configuration. |
| NBOOT0 | NBOOT0 option bit 0 (B_0x0): NBOOT01=10 1 (B_0x1): NBOOT01=11 |
| NRST_MODE | NRST pin configuration 1 (B_0x1): Reset input only: a low level on the NRST pin generates system reset; internal RESET is not propagated to the NRST pin. 2 (B_0x2): Standard GPIO: only internal RESET is possible 3 (B_0x3): Bidirectional reset: the NRST pin is configured in reset input/output (legacy) mode |
| IRHEN | Internal reset holder enable bit 0 (B_0x0): Internal resets are propagated as simple pulse on NRST pin 1 (B_0x1): Internal resets drives NRST pin low until it is seen as low level |