IN1SEL=B_0x0, IC2SEL=B_0x0, IC1SEL=B_0x0, IN2SEL=B_0x0
LPTIM configuration register 2
| IN1SEL | LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to Section125.4.3: LPTIM input and trigger mapping. 0 (B_0x0): LPTIM1_in1_mux0 1 (B_0x1): LPTIM1_in1_mux1 2 (B_0x2): LPTIM1_in1_mux2 3 (B_0x3): LPTIM1_in1_mux3 |
| IN2SEL | LPTIM input 2 selection The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. For connection details refer to Section125.4.3: LPTIM input and trigger mapping. 0 (B_0x0): LPTIM1_in2_mux0 1 (B_0x1): LPTIM1_in2_mux1 2 (B_0x2): LPTIM1_in2_mux2 3 (B_0x3): LPTIM1_in2_mux3 |
| IC1SEL | LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to Section125.4.3: LPTIM input and trigger mapping. 0 (B_0x0): LPTIM1_ic1_mux0 1 (B_0x1): LPTIM1_ic1_mux1 2 (B_0x2): LPTIM1_ic1_mux2 3 (B_0x3): LPTIM1_ic1_mux3 |
| IC2SEL | LPTIM input capture 2 selection The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture 2 to one of the available inputs. For connection details refer to Section125.4.3: LPTIM input and trigger mapping. 0 (B_0x0): LPTIM1_ic2_mux0 1 (B_0x1): LPTIM1_ic2_mux1 2 (B_0x2): LPTIM1_ic2_mux2 3 (B_0x3): LPTIM1_ic2_mux3 |