CC4E=B_0x0, CC4P=B_0x0, IC3F=B_0x0, CC4SEL=B_0x0, CC3SEL=B_0x0, CC3P=B_0x0, IC4F=B_0x0, CC3E=B_0x0, IC4PSC=B_0x0, IC3PSC=B_0x0
LPTIM capture/compare mode register 2
| CC3SEL | Capture/compare 3 selection This bitfield defines the direction of the channel input (capture) or output mode. 0 (B_0x0): CC3 channel is configured in output PWM mode 1 (B_0x1): CC3 channel is configured in input capture mode |
| CC3E | Capture/compare 3 output enable. Condition: CC3 as output: Condition: CC3 as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 3 (LPTIM2_CCR3) or not. 0 (B_0x0): Capture disabled. Writing ‘0’ to the CC3E bit resets the associated ic3_dma_req signal. 1 (B_0x1): Capture enabled. |
| CC3P | Capture/compare 3 output polarity. Condition: CC3 as output: Only bit2 is used to set polarity when output mode is enabled, bit3 is don’t care. Condition: CC3 as input: This field is used to select the IC3 polarity for capture operations. 0 (B_0x0): rising edge, circuit is sensitive to IC3 rising edge 1 (B_0x1): falling edge, circuit is sensitive to IC3 falling edge 2 (B_0x2): reserved, do not use this configuration. 3 (B_0x3): both edges, circuit is sensitive to both IC3 rising and falling edges. |
| IC3PSC | Input capture 3 prescaler This bitfield defines the ratio of the prescaler acting on the CC3 input (IC3). 0 (B_0x0): no prescaler, capture is done each time an edge is detected on the capture input 1 (B_0x1): capture is done once every 2 events 2 (B_0x2): capture is done once every 4 events 3 (B_0x3): capture is done once every 8 events |
| IC3F | Input capture 3 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. 0 (B_0x0): any external input capture signal level change is considered as a valid transition 1 (B_0x1): external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 2 (B_0x2): external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 3 (B_0x3): external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. |
| CC4SEL | Capture/compare 4 selection This bitfield defines the direction of the channel, input (capture) or output mode. 0 (B_0x0): CC4 channel is configured in output PWM mode 1 (B_0x1): CC4 channel is configured in input capture mode |
| CC4E | Capture/compare 4 output enable. Condition: CC4 as output: Condition: CC4 as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 4 (LPTIM2_CCR4) or not. 0 (B_0x0): Capture disabled. Writing ‘0’ to the CC4E bit resets the associated ic4_dma_req signal. 1 (B_0x1): Capture enabled. |
| CC4P | Capture/compare 4 output polarity. Condition: CC4 as output: Only bit2 is used to set polarity when output mode is enabled, bit3 is don’t care. Condition: CC4 as input: This field is used to select the IC4 polarity for capture operations. 0 (B_0x0): rising edge, circuit is sensitive to IC4 rising edge 1 (B_0x1): falling edge, circuit is sensitive to IC4 falling edge 2 (B_0x2): reserved, do not use this configuration. 3 (B_0x3): both edges, circuit is sensitive to both IC4 rising and falling edges. |
| IC4PSC | Input capture 4 prescaler This bitfield defines the ratio of the prescaler acting on the CC4 input (IC4). 0 (B_0x0): no prescaler, capture is done each time an edge is detected on the capture input 1 (B_0x1): capture is done once every 2 events 2 (B_0x2): capture is done once every 4 events 3 (B_0x3): capture is done once every 8 events |
| IC4F | Input capture 4 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. 0 (B_0x0): any external input capture signal level change is considered as a valid transition 1 (B_0x1): external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 2 (B_0x2): external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 3 (B_0x3): external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. |