WUFIE=B_0x0, OVRDIS=B_0x0, DDRE=B_0x0, WUS0=B_0x0, TXFTCFG=B_0x0, DMAR=B_0x0, CTSIE=B_0x0, HDSEL=B_0x0, DEP=B_0x0, RXFTCFG=B_0x0, CTSE=B_0x0, RXFTIE=B_0x0, DEM=B_0x0, DMAT=B_0x0, EIE=B_0x0, WUS1=B_0x0, RTSE=B_0x0, TXFTIE=B_0x0
LPUART control register 3
| EIE | Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NE=1 in the LPUART_ISR register). 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An interrupt is generated when FE=1 or ORE=1 or NE=1 in the LPUART_ISR register. |
| HDSEL | Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): Half-duplex mode is not selected 1 (B_0x1): Half-duplex mode is selected |
| DMAR | DMA enable receiver This bit is set/reset by software 0 (B_0x0): DMA mode is disabled for reception 1 (B_0x1): DMA mode is enabled for reception |
| DMAT | DMA enable transmitter This bit is set/reset by software 0 (B_0x0): DMA mode is disabled for transmission 1 (B_0x1): DMA mode is enabled for transmission |
| RTSE | RTS enable This bit can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): RTS hardware flow control disabled 1 (B_0x1): RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. |
| CTSE | CTS enable This bit can only be written when the LPUART is disabled (UE=0) 0 (B_0x0): CTS hardware flow control disabled 1 (B_0x1): CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. |
| CTSIE | CTS interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register |
| OVRDIS | Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE=0). Note: This control bit enables checking the communication flow w/o reading the data. 0 (B_0x0): Overrun Error Flag, ORE is set when received data is not read before receiving new data. 1 (B_0x1): Overrun functionality is disabled. If new data is received while the RXNE flag is still set |
| DDRE | DMA Disable on Reception Error This bit can only be written when the LPUART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error. 0 (B_0x0): DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. 1 (B_0x1): DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag. |
| DEM | Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): DE function is disabled. 1 (B_0x1): DE function is enabled. The DE signal is output on the RTS pin. |
| DEP | Driver enable polarity selection This bit can only be written when the LPUART is disabled (UE=0). 0 (B_0x0): DE signal is active high. 1 (B_0x1): DE signal is active low. |
| WUS0 | Wake-up from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wake-up from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UE=0). Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. 0 (B_0x0): WUF active on address match (as defined by ADD[7:0] and ADDM7) 1 (B_0x1): Reserved. |
| WUS1 | Wake-up from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wake-up from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UE=0). Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. 0 (B_0x0): WUF active on address match (as defined by ADD[7:0] and ADDM7) 1 (B_0x1): Reserved. |
| WUFIE | Wake-up from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section132.3: LPUART implementation on page1914. 0 (B_0x0): Interrupt inhibited 1 (B_0x1): USART interrupt generated whenever WUF=1 in the LPUART_ISR register |
| TXFTIE | TXFIFO threshold interrupt enable This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): A LPUART interrupt is generated when TXFIFO reaches the threshold programmed in TXFTCFG. |
| RXFTCFG | Receive FIFO threshold configuration Remaining combinations: Reserved. 0 (B_0x0): Receive FIFO reaches 1/8 of its depth. 1 (B_0x1): Receive FIFO reaches 1/4 of its depth. 3 (B_0x3): Receive FIFO reaches 3/4 of its depth. 4 (B_0x4): Receive FIFO reaches 7/8 of its depth. 5 (B_0x5): Receive FIFO becomes full. 6 (B_0x6): Receive FIFO reaches 1/2 of its depth. |
| RXFTIE | RXFIFO threshold interrupt enable This bit is set and cleared by software. 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An LPUART interrupt is generated when Receive FIFO reaches the threshold programmed in RXFTCFG. |
| TXFTCFG | TXFIFO threshold configuration Remaining combinations: Reserved. 0 (B_0x0): TXFIFO reaches 1/8 of its depth. 1 (B_0x1): TXFIFO reaches 1/4 of its depth. 3 (B_0x3): TXFIFO reaches 3/4 of its depth. 4 (B_0x4): TXFIFO reaches 7/8 of its depth. 5 (B_0x5): TXFIFO becomes empty. 6 (B_0x6): TXFIFO reaches 1/2 of its depth. |