SWS=B_0x0, MCOSEL=B_0x0, MCO2PRE=B_0x0, MCOPRE=B_0x0, MCO2SEL=B_0x0, STOPWUCK=B_0x0, SW=B_0x0
Clock configuration register
| SW | System clock switch This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows: Others: Reserved The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected. 0 (B_0x0): MSI 1 (B_0x1): HSI16 2 (B_0x2): HSE 3 (B_0x3): PLLRCLK 4 (B_0x4): LSI 5 (B_0x5): LSE |
| SWS | System clock switch status This bitfield is controlled by hardware to indicate the clock source used as system clock: Others: Reserved 0 (B_0x0): MSI 1 (B_0x1): HSI16 2 (B_0x2): HSE 3 (B_0x3): PLLRCLK 4 (B_0x4): LSI 5 (B_0x5): LSE |
| HPRE | AHB prescaler This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows: 0xxx: 1 Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section14.1.4: Dynamic voltage scaling management). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. 8 (B_0x8): 2 9 (B_0x9): 4 10 (B_0xA): 8 11 (B_0xB): 16 12 (B_0xC): 64 13 (B_0xD): 128 14 (B_0xE): 256 15 (B_0xF): 512 |
| PPRE | APB prescaler This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows: 0xx: 1 4 (B_0x4): 2 5 (B_0x5): 4 6 (B_0x6): 8 7 (B_0x7): 16 |
| STOPWUCK | Wake-up from Stop and CSS backup clock selection Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=10) or a switch on HSE is requested (SW=10). 0 (B_0x0): MSI oscillator selected as wake-up from stop clock and CSS backup clock. 1 (B_0x1): HSI16 oscillator selected as wake-up from stop clock and CSS backup clock |
| MCO2SEL | Microcontroller clock output 2 clock selector This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching. 0 (B_0x0): no clock, MCO2 output disabled 1 (B_0x1): SYSCLK 2 (B_0x2): MSI 3 (B_0x3): HSI16 4 (B_0x4): HSE 5 (B_0x5): PLLRCLK 6 (B_0x6): LSI 7 (B_0x7): LSE 8 (B_0x8): HSI48 9 (B_0x9): RTCCLK 10 (B_0xA): RTC WAKEUP |
| MCO2PRE | Microcontroller clock output 2 prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows: … Others: reserved It is highly recommended to set this field before the MCO2 output is enabled. 0 (B_0x0): 1 1 (B_0x1): 2 2 (B_0x2): 4 7 (B_0x7): 128 8 (B_0x8): 256 9 (B_0x9): 512 10 (B_0xA): 1024 |
| MCOSEL | Microcontroller clock output clock selector This bitfield is controlled by software. It sets the clock selector for MCO output as follows: Others: Reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. 0 (B_0x0): no clock, MCO output disabled 1 (B_0x1): SYSCLK 2 (B_0x2): MSI 3 (B_0x3): HSI16 4 (B_0x4): HSE 5 (B_0x5): PLLRCLK 6 (B_0x6): LSI 7 (B_0x7): LSE 8 (B_0x8): HSI48 9 (B_0x9): RTCCLK 10 (B_0xA): RTC WAKEUP |
| MCOPRE | Microcontroller clock output prescaler This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows: … Others: reserved It is highly recommended to set this field before the MCO output is enabled. 0 (B_0x0): 1 1 (B_0x1): 2 2 (B_0x2): 4 7 (B_0x7): 128 8 (B_0x8): 256 9 (B_0x9): 512 10 (B_0xA): 1024 |