LSERDYIE=B_0x0, MSIRDYIE=B_0x0, HSIRDYIE=B_0x0, PLLRDYIE=B_0x0, HSI48RDYIE=B_0x0, LSIRDYIE=B_0x0, LSECSSIE=B_0x0, HSERDYIE=B_0x0
Clock interrupt enable register
| LSIRDYIE | LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization: 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LSERDYIE | LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization: 0 (B_0x0): Disable 1 (B_0x1): Enable |
| MSIRDYIE | MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. 0 (B_0x0): MSI ready interrupt disabled 1 (B_0x1): MSI ready interrupt enabled |
| HSIRDYIE | HSI16 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization: 0 (B_0x0): Disable 1 (B_0x1): Enable |
| HSERDYIE | HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization: 0 (B_0x0): Disable 1 (B_0x1): Enable |
| PLLRDYIE | PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock: 0 (B_0x0): Disable 1 (B_0x1): Enable |
| LSECSSIE | LSE clock security system interrupt enable Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE. 0 (B_0x0): Clock security interrupt caused by LSE clock failure disabled 1 (B_0x1): Clock security interrupt caused by LSE clock failure enabled |
| HSI48RDYIE | HSI48 ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator. 0 (B_0x0): HSI48 ready interrupt disabled 1 (B_0x1): HSI48 ready interrupt enabled |