HSERDY=B_0x0, PLLRDY=B_0x0, HSIASFS=B_0x0, CSSON=B_0x0, HSIRDY=B_0x0, HSIKERON=B_0x0, MSIRDY=B_0x0, MSIPLLEN=B_0x0, HSEBYP=B_0x0, MSIRANGE=B_0x0, HSION=B_0x0, MSIRGSEL=B_0x0, HSEON=B_0x0, PLLON=B_0x0, MSION=B_0x0
Clock control register
| MSION | MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock. 0 (B_0x0): MSI oscillator OFF 1 (B_0x1): MSI oscillator ON |
| MSIRDY | MSI clock ready flag This bit is set by hardware to indicate that the MSI oscillator is stable. Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. 0 (B_0x0): MSI oscillator not ready 1 (B_0x1): MSI oscillator ready |
| MSIPLLEN | MSI clock PLL enable Set and cleared by software to enable/ disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register). 0 (B_0x0): MSI PLL OFF 1 (B_0x1): MSI PLL ON |
| MSIRGSEL | MSI clock range selection Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register. 0 (B_0x0): MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register 1 (B_0x1): MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register |
| MSIRANGE | MSI clock ranges These bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set.12 frequency ranges are available: others: not allowed (hardware write protection) Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0) 0 (B_0x0): range 0 around 1001kHz 1 (B_0x1): range 1 around 2001kHz 2 (B_0x2): range 2 around 4001kHz 3 (B_0x3): range 3 around 8001kHz 4 (B_0x4): range 4 around 1M1Hz 5 (B_0x5): range 5 around 21MHz 6 (B_0x6): range 6 around 41MHz (reset value) 7 (B_0x7): range 7 around 81MHz 8 (B_0x8): range 8 around 161MHz 9 (B_0x9): range 9 around 241MHz 10 (B_0xA): range 10 around 321MHz 11 (B_0xB): range 11 around 481MHz |
| HSION | HSI16 clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock). 0 (B_0x0): HSI16 oscillator OFF 1 (B_0x1): HSI16 oscillator ON |
| HSIKERON | HSI16 always enable for peripheral kernels. Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows avoiding to slow down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value. 0 (B_0x0): No effect on HSI16 oscillator. 1 (B_0x1): HSI16 oscillator is forced ON even in Stop mode. |
| HSIRDY | HSI16 clock ready flag Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION. Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles. 0 (B_0x0): HSI16 oscillator not ready 1 (B_0x1): HSI16 oscillator ready |
| HSIASFS | HSI16 automatic start from Stop Set and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI16 is parallel of the system wake-up. 0 (B_0x0): HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wake-up clock. 1 (B_0x1): HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wake-up clock. |
| HSEON | HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0 (B_0x0): HSE oscillator OFF 1 (B_0x1): HSE oscillator ON |
| HSERDY | HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles. 0 (B_0x0): HSE oscillator not ready 1 (B_0x1): HSE oscillator ready |
| HSEBYP | HSE crystal oscillator bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0 (B_0x0): HSE crystal oscillator not bypassed 1 (B_0x1): HSE crystal oscillator bypassed with external clock |
| CSSON | Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 0 (B_0x0): Clock security system OFF (clock detector OFF) 1 (B_0x1): Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not). |
| PLLON | PLL enable Set and cleared by software to enable the PLL. Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock. 0 (B_0x0): PLL OFF 1 (B_0x1): PLL ON |
| PLLRDY | PLL clock ready flag Set by hardware to indicate that the PLL is locked. 0 (B_0x0): PLL unlocked 1 (B_0x1): PLL locked |