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STMicroelectronics /STM32U083 /RCC /RCC_DBGCFGR

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Interpret as RCC_DBGCFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBGEN 0 (B_0x0)DBGRST

DBGRST=B_0x0, DBGEN=B_0x0

Description

Debug configuration register

Fields

DBGEN

Debug support clock enable Set and cleared by software.

0 (B_0x0): Disable

1 (B_0x1): Enable
DBGRST

Debug support reset Set and cleared by software.

0 (B_0x0): No effect

1 (B_0x1): Reset DBG

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data