PLLM=B_0x0, PLLSRC=B_0x0, PLLQEN=B_0x0, PLLPEN=B_0x0, PLLN=B_0x0, PLLREN=B_0x0
PLL configuration register
| PLLSRC | PLL input clock source This bit is controlled by software to select PLL clock source, as follows: The bitfield can be written only when the PLL is disabled. When the PLL is not used, selecting 00 allows saving power. 0 (B_0x0): No clock 1 (B_0x1): MSI 2 (B_0x2): HSI16 3 (B_0x3): HSE |
| PLLM | Division factor M of the PLL input clock divider This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz. 0 (B_0x0): 1 1 (B_0x1): 2 2 (B_0x2): 3 3 (B_0x3): 4 4 (B_0x4): 5 5 (B_0x5): 6 6 (B_0x6): 7 7 (B_0x7): 8 |
| PLLN | PLL frequency multiplication factor N This bit is controlled by software to set the division factor of the fVCO feedback divider (that determines the PLL multiplication ratio) as follows: … … The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz. 0 (B_0x0): Invalid 4 (B_0x4): 4 5 (B_0x5): 5 126 (B_0x7E): 126 127 (B_0x7F): 127 |
| PLLPEN | PLLPCLK clock output enable This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: Disabling the PLLPCLK clock output, when not used, allows saving power. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| PLLP | PLL VCO division factor P for PLLPCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: … The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. 1 (B_0x1): 2 31 (B_0x1F): 32 |
| PLLQEN | PLLQCLK clock output enable This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: Disabling the PLLQCLK clock output, when not used, allows saving power. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| PLLQ | PLL VCO division factor Q for PLLQCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock. 1 (B_0x1): 2 2 (B_0x2): 3 3 (B_0x3): 4 4 (B_0x4): 5 5 (B_0x5): 6 6 (B_0x6): 7 7 (B_0x7): 8 |
| PLLREN | PLLRCLK clock output enable This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. Disabling the PLLRCLK clock output, when not used, allows saving power. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| PLLR | PLL VCO division factor R for PLLRCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: The bitfield can be written only when the PLL is disabled. The PLLRCLK clock can be selected as system clock. Caution: The software must set this bitfield so as not to exceed 122MHz on this clock. 1 (B_0x1): 2 2 (B_0x2): 3 3 (B_0x3): 4 4 (B_0x4): 5 5 (B_0x5): 6 6 (B_0x6): 7 7 (B_0x7): 8 |