STMicroelectronics /STM32U083 /RNG /RNG_CR

True random number generator enable

0 (B_0x0): True random number generator is disabled. Analog noise sources are powered off and logic clocked by the RNG clock is gated.

1 (B_0x1): True random number generator is enabled.

Interrupt enable

0 (B_0x0): RNG interrupt is disabled

1 (B_0x1): RNG interrupt is enabled. An interrupt is pending as soon as DRDY1=11, SEIS1=11 or CEIS1=11 in the RNG_SR register.

Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, that is to enable or disable CED, the RNG must be disabled. Writing this bit is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11.

0 (B_0x0): Clock error detection enabled

1 (B_0x1): Clock error detection is disabled

Auto reset disable When auto-reset is enabled the application still need to clear the SEIS bit after a noise source error. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11.

0 (B_0x0): When a noise source error occurs RNG performs an automatic reset to clear the SECS bit.

1 (B_0x1): When a noise source error occurs the application must reset RNG by writing CONDRST to 1 then to 0, in order to restart random number generation.

RNG configuration 3 Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details. If the NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG.

NIST custom two conditioning loops are performed and 256 bits of noise source are used. Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11.

0 (B_0x0): Hardware default values for NIST compliant RNG. In this configuration per 128-bit output

1 (B_0x1): Custom values for NIST compliant RNG. See Section120.6: RNG entropy source validation for proposed configuration.

RNG configuration 2 Reserved to the RNG configuration (bitfield 2). Bit 13 can be set when RNG power consumption is critical. See Section120.3.8: RNG low-power use. Refer to the RNG_CONFIG1 bitfield for details.

Clock divider factor This value used to configure an internal programmable divider (from 1 to 16) acting on the incoming RNG clock. These bits can be written only when the core is disabled (RNGEN1=10). … Writing these bits is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11.

0 (B_0x0): internal RNG clock after divider is similar to incoming RNG clock.

1 (B_0x1): two RNG clock cycles per internal RNG clock.

2 (B_0x2): 2² (= 4) RNG clock cycles per internal RNG clock.

15 (B_0xF): 2¹⁵ RNG clock cycles per internal clock (for example. an incoming 481MHz RNG clock becomes a 1.51kHz internal RNG clock)

RNG configuration 1 Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended value documented in Section120.6: RNG entropy source validation. Writing any bit of RNG_CONFIG1 is taken into account only if the CONDRST bit is set to 1 in the same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK1=11.

Conditioning soft reset Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_HTCR are not changed by CONDRST. This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be written. When CONDRST is set to 0 by the software, its value goes to 0 when the reset process is done. It takes about 2 AHB clock cycles + 2 RNG clock cycles.

RNG Config lock This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset.

0 (B_0x0): Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are allowed.

1 (B_0x1): Writes to the RNG_HTCR and RNG_CR configuration bits [29:4] are ignored until the next RNG reset.