I2C_PB7_FMP=B_0x0, I2C_PB8_FMP=B_0x0, IR_POL=B_0x0, PA11_RMP=B_0x0, PA12_RMP=B_0x0, IR_MOD=B_0x0, BOOSTEN=B_0x0, I2C_PA9_FMP=B_0x0, I2C_PA10_FMP=B_0x0, I2C_PB6_FMP=B_0x0, I2C_PB9_FMP=B_0x0, I2C3_FMP=B_0x0
SYSCFG configuration register 1
| MEM_MODE | Memory mapping selection bits These bits are set and cleared by software. They control the memory internal mapping at address 0x000010000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section12.5: Boot configuration for more details. X0: Main flash memory mapped at 0x000010000 1 (B_0x1): System flash memory mapped at 0x000010000 3 (B_0x3): Embedded SRAM mapped at 0x000010000 |
| PA11_RMP | PA11 pin remapping This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port. 0 (B_0x0): No remap (PA11) 1 (B_0x1): Remap (PA9) |
| PA12_RMP | PA12 pin remapping This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port. 0 (B_0x0): No remap (PA12) 1 (B_0x1): Remap (PA10) |
| IR_POL | IR output polarity selection 0 (B_0x0): Output of IRTIM (IR_OUT) is not inverted 1 (B_0x1): Output of IRTIM (IR_OUT) is inverted |
| IR_MOD | IR Modulation Envelope signal selection This bitfield selects the signal for IR modulation envelope: 0 (B_0x0): TIM16 1 (B_0x1): USART1 2 (B_0x2): USART2 |
| BOOSTEN | I/O analog switch voltage booster enable This bit selects the way of supplying I/O analog switches: When using the analog inputs , setting to 0 is recommended for high VDD, setting to 1 for low VDD (less than 2.4 V). 0 (B_0x0): VDD 1 (B_0x1): Dedicated voltage booster (supplied by VDD) |
| I2C_PB6_FMP | Fast Mode Plus (FM+) enable for PB6 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C_PB7_FMP | Fast Mode Plus (FM+) enable for PB7 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C_PB8_FMP | Fast Mode Plus (FM+) enable for PB8 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C_PB9_FMP | Fast Mode Plus (FM+) enable for PB9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C_PA9_FMP | Fast Mode Plus (FM+) enable for PA9 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C_PA10_FMP | Fast Mode Plus (FM+) enable for PA10 This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port. With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0 (B_0x0): Disable 1 (B_0x1): Enable |
| I2C3_FMP | Fast Mode Plus (FM+) enable for I2C3 This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers. With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored. Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead. 0 (B_0x0): Disable 1 (B_0x1): Enable |