CC4S=B_0x0, CC3S=B_0x0
TIM1 capture/compare mode register 2
| CC3S | Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 (B_0x0): CC3 channel is configured as output 1 (B_0x1): CC3 channel is configured as input, IC3 is mapped on TI3 2 (B_0x2): CC3 channel is configured as input, IC3 is mapped on TI4 3 (B_0x3): CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| IC3PSC | Input capture 3 prescaler Refer to IC1PSC[1:0] description. |
| IC3F | Input capture 3 filter Refer to IC1F[3:0] description. |
| CC4S | Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 0 (B_0x0): CC4 channel is configured as output 1 (B_0x1): CC4 channel is configured as input, IC4 is mapped on TI4 2 (B_0x2): CC4 channel is configured as input, IC4 is mapped on TI3 3 (B_0x3): CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| IC4PSC | Input capture 4 prescaler Refer to IC1PSC[1:0] description. |
| IC4F | Input capture 4 filter Refer to IC1F[3:0] description. |